1. Field of the Invention
The present invention generally relates to a microprocessor having a store buffer, and more particularly to a microprocessor in which data is written into an external memory through a store buffer independently of another instruction process.
2. Description of the Related Art
Recently, there has been considerable activity in the development of a microprocessor having a built-in cache and/or a store buffer, which is provided for reducing the time it takes to access an external memory. Generally, such a microprocessor uses ring information for protecting the contents of the external memory from being damaged. Ring information is provided for each area of the external memory. For example, ring information defines four different levels of `0`, `1`, `2` and `3`, in which ring level `0` is the highest. Ring information is used for discriminating a privileged level of an operating system against a non-privileged level thereof or preventing the contents of the external memory from being mistakenly accessed by a task in a multi-task processing. Ring information on a program which is being processed is represented in a program status word (PSW). For example, when an area of the external memory is accessed by a program (instruction), ring information on that area is compared with the current ring information described in the program status word. For example, when the area to be accessed has ring level `2` and the current ring information represents ring level `2`, the access to the area is inhibited.
A microprocessor having a cache memory is known. Such a microprocessor has a mode in which data is written into a cache memory and an external memory at the same time. Generally, it takes a long time to write data into the external memory. It is noted that an instruction cycle in the microprocessor must be stopped until an instruction to write data into the external memory is completed. This deteriorates performance of the microprocessor.
From this viewpoint, a microprocessor having a store buffer in addition to the cache memory has been proposed. In such a microprocessor, when data is written into the external memory, the data and a corresponding address of the external memory are written into the store buffer by an instruction to write data into the external memory issued by a central processing unit (CPU). The execution of this instruction is completed when the address and data are written into the store buffer. Thus, the microprocessor can execute another instruction. On the other hand, when a bus provided between the microprocessor and the external memory becomes available, data is read out from the store buffer and then written into the external memory independently of the execution of another instruction by the CPU.
When an error occurs while the data is being read out from the store buffer and written into the external memory, an exception processing request for processing such an error takes place in asynchronism with a subsequent instruction which is generated after the instruction to write data into the external memory is completed. There is a possibility that a different exception processing request occurs when a subsequent instruction is being executed while the exception processing request for processing the above-mentioned error is being processed. From this point of view, it is necessary to consider priority between these different exception processing requests.
In the case where the microprocessor is designed so that the data write process using the store buffer is independent of another instruction, it is impossible to try to execute the instruction to write data into the external memory again from the beginning thereof when an error occurs while the data is being written into the external memory. This is because the instruction to write data into the external memory is completed when the data and associated address are written into the store buffer. For this reason, when an error is detected while data is being read out from the store buffer and transferred to the external memory, some information is saved in a predetermined area together with the program status word and an instruction address to which the process returns. For example, the above-mentioned information to be saved includes an instruction address of the instruction to write data into the external memory, an operand address, operand data and control information on operand access. After the operating system removes the cause of error, data is read out from the store buffer and written into the external memory in accordance with the information to be saved. The control information on operand access includes an operand size and information whether or not it is necessary to translate a logical (virtual) address into a physical address.
Conventionally, ring information described in the program status word which is saved in the predetermined area, is used when trying to write data into the external memory again after an error occurs. The saved program status word relates to an address to which the process returns. Thus, the saved program status word has ring information indicating a ring level obtained when an instruction which is being processed in the store buffer at the time of detecting an error is completed. This ring level must be maintained until writing data into the external memory is retried. If the ring level is changed, some problems occur when writing data into the external memory is tried again. For example, a data write inhibit area of the external memory may be accessed in error so that the contents of the area are damaged.
For this reason, it is required to provide priority between the exception processes with a limitation. For example, an exception processing request other than an exception process request for processing an error occurring in the store buffer is accepted ahead of the latter exception process. However, when the former exception processing request is handled by the operating system, which generally has the highest ring level, the ring information described in the program status word is changed by information relating to the operating system. Thus the program status word to be saved by the exception process request for processing errors in the store buffer which occurs after the operating system runs, has information relating to the operating system. That is, in the program status word to be saved, no information is left which is obtained when reading out data from the store buffer and writing the same into the external memory.
Alternatively, it is conceivable to accept the exception processing request for processing an error occurring in the store buffer ahead of other exception processing requests. In this case, when an instruction to change ring information in the program status word is generated, the CPU cannot execute this instruction until the store buffer becomes available. For this reason, the microprocessor operates at a decreased processing speed. In addition, when the above-mentioned instruction has a priority level higher than the exception processing request for processing an error occurring in the store buffer, this instruction is not allowed to be processed ahead of the exception processing process. Further, there is a problem. It is now assumed that an instruction has a basic length of two bytes and must have an instruction address having an even number without exception. If a branch instruction indicates an odd number branch address, an associated exception process request occurs. In this exception process, an address of the branch instruction and the inappropriate branch address must be saved. When the exception processing request for processing an error occurring in the store buffer is accepted ahead of the exception processing request for processing the odd number branch address, information relating to the latter exception processing request is handled as information about the former exception processing request. As described above, a limitation provided to priority between the different exception processing requests causes various problems.